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FC-BGA substrates

FC-BGA (flip chip ball grid array) on a high density semiconductor package substrate allows high speed LSI chips with more functions.

We have developed ultra high density wiring substrates with our original microfabrication and build-up wiring technologies, offering products supporting current semiconductor microfabrication.

For a growing demand for LSIs for automotive SoC or high-end processors (server, AI, network) as well as for PCs or game devices, we provide comprehensive support from substrate design to production.
Solutions for lead-free and halogen-free products are also available.

Structure & Manufacturing process

Structure of FC-BGA

Structure of FC-BGA

Manufacturing process

  • Core Process

    Drill holes in the core material and plate it with copper. Then remove the copper except for a circuit pattern area.

  • →
  • Build-up processing

    Expose a circuit pattern to directly form circuit with copper plating. Repeat this treatment and laminate (build up)

  • →
  • Outer layer Process

    After applying solder resist, place solder bumps where LSI chips (die) will be mounted. After cutting into each pieces, inspect appearance and electric characteristics.

Applications

  • Network device
    (ASIC)
  • Server / PC
    (CPU)
  • AI Processor
  • Automotive
    (Infotainment / ADAS)
  • Home Game Console
    (Soc)
  • Graphic Processing Unit
    (GPU)

Product Lineup

  • FC-BGA
  • FC-LGA
  • Multi-chip FC-BGA
  • Ultra-multilayer FC-BGA
  • Coreless FC-BGA
  • 2.5D FC-BGA
  • 2.1D FC-BGA

Roadmap

Build up

Core

※ Please contact us individually about the materials for prototyping/evaluation.

Features

High-density Support

  • Hyper Build-up
    6 stack VIA
    Land / Via = 85 / 60μm
  • Structure of Via
    10 stack VIA
    Land / Via = 100 / 60μmm
  • SR Planarization
    Stable SR opening size
    Uniform SR Opening shape
  • Fine-pitch Core
    Land / Thtough Hole
    dia = 205 / 105μm

Fine-pitch FC bump

  • FC bump
    Pitch = 150μm
  • FC bump
    Pitch = 120μm

Low copper roughness treatment

  • Ra:400-250nm
  • Ra:200-100nm

Higher Pin Account / Ultra Fine Wiring

  • Fine Pitch Patterning (Semi Additive Process)
    Line / Space = 10 / 10μm
  • Fine Pitch Patterning (Subtractive Process)
    Line / Space = 30 / 30μm

Support for design and simulation

Designing process flow

Simulation service

Heat transmission analysis example

  • Characteristic impedance
  • Heat transmission analysis
  • Stress analysis
  • Electromagnetic field analysis

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