Jan 17, 2011
for 14nm Photomask Process Development
Tokyo - Jan. 17, 2011-- Toppan Printing Co., Ltd. (Toppan Printing; Head office: Chiyoda-ku, Tokyo; President & CEO: Shingo Kaneko) announced today that it has extended a joint development agreement with IBM for leading-edge photomask process, covering the 14 nanometer technology node for logic devices. The development work will take place at IBM’ s photomask facility in Essex Junction, VT., and Toppan’ s Asaka photomask facility in Niiza, Saitama, Japan, from January 2011 through 2012.
This new agreement represents the continuation of a partnership that began in 2005 with 45nm photomask process development, and has progressed through the 32nm, 28nm, 22nm, and 20nm technology nodes. The jointly developed photomask manufacturing processes have been essential contributors to advanced wafer process development by IBM and its partners in East Fishkill and Albany, NY.
Several new technologies including extreme ultraviolet (EUV) have been evaluated for next-generation lithography solutions. While Toppan Printing is committed to supporting those developments, IBM has successfully developed a technology roadmap for ArF immersion lithography*, a current mainstream technology, that allows its extension to the 14nm generation through the use of IBM’ s highly regarded resolution enhancement techniques. As a result, Toppan and IBM will focus their joint development efforts on ArF immersion lithography for the 14nm node.
The 14nm logic technology node is likely to be the final node capable of being produced with optical lithography alone, and may prove to be an early transition point into EUV development. Future nodes are expected to deploy EUV lithography in order to print features beyond the diffraction limit associated with 193nm lithography.
"This newest joint process development agreement with Toppan Printing builds upon the success that our two companies have enjoyed while working together over the past several years. This newest agreement will help ensure we can continue to develop the leadership in semiconductor technology that is critical for IBM systems, our OEM semiconductor clients, and our JDA partners, " said Michael Cadigan, General Manager, IBM Microelectronics. "This collaborative effort builds upon our joint progress at 45nm, 32/28nm and 22/20nm, and sets us on a path to deliver the photomasks needed for the next-generation chip manufacturing production."
"We are proud to continue our close working relationship with IBM, a world technology leader in the semiconductor industry, and to expand the scope of our development work to the emerging 14nm technology node," said Toshiro Masuda, Managing Director, Deputy Head of Electronics Division, Toppan Printing. "Over the past five years of collaboration, our two companies have built unique development capabilities, and a strong culture of teamwork. We will continue to operate at the forefront of leading-edge photomask technology development, and contribute to the further evolution of the semiconductor industry."
Toppan-IBM Joint Development Project in Advanced Photomasks
Toppan Printing and IBM started joint development of photomasks for 45nm semiconductors in 2005, and expanded the scope of their activities to include 32nm/28nm development in 2008 and 22nm/20nm in 2009. This joint development effort with industry leader IBM is part of Toppan Printing’ s commitment to providing advanced photomasks to its customers around the world in a timely and efficient manner. Toppan’ s latest photomask technology solution will continue to accommodate the wafer requirements for advanced double patterning* and source mask optimization (SMO)*.
About Toppan Printing’ s Photomask Business
Toppan Printing is the world’ s premier photomask manufacturer. The company supports the global semiconductor industry, from the initial launch of the semiconductor manufacturing process through commercial production, by providing state-of-the-art photomask technology. For more information, visit www.toppan.co.jp.
(*1) Immersion lithography
Immersion lithography is a resolution enhancement technology (RET) that places a liquid, such as ultra-pure water, between the lens of the scanner and the silicon wafer to achieve an improved refractive index.
(*2) Double patterning
Double patterning is an exposure technology that separates one high-density circuit pattern into two lower-density patterns that are placed on separate photomasks. By exposing the two lower-density patterns sequentially on one wafer, high-density patterns can be made.
(*3) SMO (Source Mask Optimization)
SMO extends conventional lithographic techniques to finer patterning capabilities by precisely shaping the scanner’ s illumination and mask pattern. It is expected to help make ArF immersion lithography a practical patterning technology for 22nm circuits and beyond.